| Power supply schemes•VDD: external power supply for I/Os and the internal regulator. It is provided externallythrough VDD pins, and can be 2.0 to 3.6 V.•VDDA = 2.0 to 3.6 V:–external analog power supplies for Reset blocks, RCs and PLL–supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to beapplied to VDDA is 2.4 V when the 12-bit ADC and DAC are used).•VDDSD12 and VDDSD3 = 2.2 to 3.6 V: supply voltages for SDADC1/2 and SDADCD3sigma delta ADCs. Independent from VDD/VDDA.•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator andbackup registers when VDD is not present.3.7.2Power supply supervisor•The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry.It is always active, and ensures proper operation starting from/down to 2 V. The deviceremains in reset mode when VDD is below a specified threshold, VPOR/PDR, without theneed for an external reset circuit. The POR monitors only the VDD supply voltage.During the startup phase it is required that VDDA should arrive first and be greater thanor equal to VDD.•The PDR monitors both the VDD and VDDA supply voltages, however the VDDA powersupply supervisor can be disabled (by programming a dedicated Option bit) to reducethe power consumption if the application design ensures that VDDA is higher than orequal to VDD.The device features an embedded programmable voltage detector (PVD) that monitors theVDD power supply and compares it to the VPVD threshold. An interrupt can be generatedwhen VDD drops below the VPVD threshold and/or when VDD is higher than the VPVDthreshold. The interrupt service routine can then generate a warning message and/or putthe MCU into a safe state. The PVD is enabled by softwa |
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